1. Field of the Invention
The present invention relates to a static random access memory (SRAM) unit cell, and more particularly, to a SRAM unit cell having two varactors respectively connected to two storage nodes.
2. Description of the Prior Art
The static random access memory (SRAM) is a type of memory that is able to store data without constantly refreshing them as long as it is supplied with power. Because of its high access speed and low power consumption, SRAM has been applied to electronic devices, such as a notebook, a portable device or a video game console.
Conventional SRAM device includes a six-transistor (6-T) cell with two cross-coupled inverters. Each inverter includes a pull-up transistor and a pull-down transistor. A storage node of each inverter is connected to the gates of both transistors of the other inverter. Also, the storage nodes are respectively coupled to two bit lines through two pass gate transistors. The gates of the pass gate transistors are connected to a common word line. During read operation, the bit lines are pre-charged to a high voltage level. Then, the bit lines are floated, and the word line is used to turn on the pass gate transistors. The voltage level of one of the bit lines is pulled down by a low voltage state “0” stored in one of the storage nodes, so that a voltage difference in the bit lines can be detected, and the logic states at the storage nodes can be read. During write operation, the bit lines are provided with programming voltages, and the word line is used to turn on the pass gate transistors, so that the voltages at the storage nodes can be programmed.
However, with the decrease of the high voltage level and the miniaturization of the SRAM device, the read operation of the SRAM device is easily disturbed and fails during high speed read, and the data in storage nodes are easily flipped due to charges from radioactive materials or cosmic rays, thereby increasing the soft error rate (SER) of the SRAM device. Although the storage nodes respectively connected to capacitors with the same capacitance has been developed to effectively store the data and reduce read failure and the SER, this design would reduce the speed of writing the data. Thus, to provide a better SRAM is always in need in this field.